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a
LC2MOS +3.3 V/+5 V, Low Power, Quad 12-Bit DAC AD7564
FUNCTIONAL BLOCK DIAGRAM
NC AGND V DD DGND V REF D V REF C V REFB VREF A R FB A
FEATURES Four 12-Bit DACs in One Package 4-Quadrant Multiplication Separate References Single Supply Operation Guaranteed Specifications with +3.3 V/+5 V Supply Low Power Versatile Serial Interface Simultaneous Update Capability Reset Function 28-Pin SOIC, SSOP and DIP Packages APPLICATIONS Process Control Portable Instrumentation General Purpose Test Equipment
FSIN CLKIN SDIN
INPUT LATCH A
12
DAC A LATCH
12
DAC A
IOUT1 A IOUT2 A RFB B
INPUT LATCH B
12
DAC B LATCH
12
DAC B
IOUT1 B IOUT2 B RFB C
INPUT LATCH C
12
DAC C LATCH
12
DAC C
IOUT1 C IOUT2 C R FBD
INPUT LATCH D 12
12
DAC D LATCH
12
DAC D
IOUT1 D IOUT2 D
CONTROL LOGIC + INPUT SHIFT REGISTER
CLR LDAC
AD7564
SDOUT
A0 A1
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7564 contains four 12-bit DACs in one monolithic device. The DACs are standard current output with separate VREF, IOUT1, IOUT2 and RFB terminals. These DACs operate from a single +3.3 V to +5 V supply. The AD7564 is a serial input device. Data is loaded using FSIN, CLKIN and SDIN. Two address pins A0 and A1 set up a device address, and this feature may be used to simplify device loading in a multi-DAC environment. Alternatively, A0 and A1 can be ignored and the serial out capability used to configure a daisy-chained system. All DACs can be simultaneously updated using the asynchronous LDAC input, and they can be cleared by asserting the asynchronous CLR input. The device is packaged in 28-pin SOIC, SSOP and DIP packages.
1. The AD7564 contains four 12-bit current output DACs with separate VREF inputs. 2. The AD7564 can be operated from a single +3.3 V to +5 V supply. 3. Simultaneous update capability and reset function are available. 4. The AD7564 features a fast, versatile serial interface compatible with modern 3 V and 5 V microprocessors and microcomputers. 5. Low power, 50 W at 5 V and 33 W at 3.3 V.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD7564-SPECIFICATIONSA to I (V = +4.75 V to +5.25 V; I
Normal Mode
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error +25C TMIN to TMAX Gain Temperature Coefficient2 Output Leakage Current IOUT1 @ +25C TMIN to TMAX REFERENCE INPUT Input Resistance Ladder Resistance Mismatch DIGITAL INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance2 DIGITAL OUTPUT (SDOUT) Output Low Voltage (VOL) Output High Voltage (VOH) POWER REQUIREMENTS VDD Range Power Supply Rejection2 Gain/VDD IDD
DD OUT1
OUT1D
= IOUT2A = IOUT2D = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX,
Test Conditions/Comments 1 LSB = VREF/212 = 2.44 mV when VREF = 10 V All Grades Guaranteed Monotonic Over Temperature
unless otherwise noted)
B Grade1 12 0.5 0.5 4 5 2 5 Units Bits LSB max LSB max LSBs max LSBs max ppm FSR/C typ ppm FSR/C max
10 50 6 13 2 2.4 0.8 1 10 0.4 4.0 4.75/5.25 -75 10
nA max nA max k min k max % max V min V max A max pF max V max V min V min/V max dB typ A max Load Circuit as in Figure 2. Typical Input Resistance = 9.5 k Typically 0.6%
Part Functions from 3.3 V to 5.25 V
VINH = VDD, VINL = 0 V At Input Levels of 0.8 V and 2.4 V, IDD is Typically 2 mA.
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Not production tested. Guaranteed by characterization at initial product release. Specifications subject to change without notice.
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REV. A
AD7564 Biased Mode1
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error +25C TMIN to TMAX Gain Temperature Coefficient3 Output Leakage Current IOUT1 @ +25C TMIN to TMAX Input Resistance @ IOUT2 Pins DIGITAL INPUTS VINH, Input High Voltage @ VDD = +5 V VINH, Input High Voltage @ VDD = +3.3 V VINL, Input Low Voltage @ VDD = +5 V VINL, Input Low Voltage @ VDD = +3.3 V IINH, Input Current CIN, Input Capacitance3 DIGITAL OUTPUT (SDOUT) Output Low Voltage (VOL) Output Low Voltage (VOL) Output High Voltage (VOH) Output High Voltage (VOH) POWER REQUIREMENTS VDD Range Power Supply Sensitivity3 Gain/VDD IDD
(VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = 1.23 V; AGND = 0 V; VREF = 0 V to 2.45 V; TA = TMIN to TMAX, unless otherwise noted)
A Grade2 12 1 0.9 4 5 2 5 Units Bits LSB max LSB max Test Conditions/Comments 1 LSB = (VIOUT2 - VREF)/212 = 300 V when VIOUT2 = 1.23 V and VREF = 0 V All Grades Guaranteed Monotonic Over Temperature
LSBs max LSBs max ppm FSR/C typ ppm FSR/C max See Terminology Section
10 50 6 2.4 2.1 0.8 0.6 1 10 0.4 0.2 4.0 VDD - 0.2 3/5.5 -75 10
nA max nA max k min V min V min V max V max A max pF max V max V max V min V min V min/V max dB typ A max Load Circuit as in Figure 2. VDD = +5 V VDD = +3.3 V VDD = +5 V VDD = +3.3 V This Varies with DAC Input Code
VINH = VDD - 0.1 V min, VINL = 0.1 V max; SDOUT Open Circuit IDD is typically 2 mA with VDD = +5 V, VINH = 2.4 V min, VINL = 0.8 V max; SDOUT Open Circuit
NOTES 1 These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a "-B" suffix (for example: AD7564AR-B). Figure 19 is an example of Biased Mode Operation. 2 Temperature ranges is as follows: A Version: -40C to +85C. 3 Not production tested. Guaranteed by characterization at initial product release. Specifications subject to change without notice.
REV. A
-3-
AD7564 AC Performance Characteristics Normal Mode
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Channel-to-Channel Isolation Digital Crosstalk Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density @ 1 kHz
(VDD = +4.75 V to +5.25 V; VIOUT1 = VIOUT2 = AGND = 0 V. VREF = 6 V rms, 1 kHz sine wave; DAC output op amp is AD843; TA = TMIN to TMAX, unless otherwise noted. These characteristics are included for Design Guidance and are not subject to test.)
B Grade 550 35 -70 60 30 -76 5 5 -83 30 Units ns typ nV-s typ dB max pF max pF max dB typ nV-s typ nV-s typ dB typ nV/Hz typ Test Conditions/Comments To 0.01% of Full-Scale Range. DAC Latch Alternately Loaded with All 0s and All 1s Measured with VREF = 0 V. DAC Register Alternately Loaded with All 0s and All 1s VREF = 20 V p-p, 10 kHz Sine Wave. DAC Latch Loaded with All 0s All 1s Loaded to DAC All 0s Loaded to DAC Feedthrough from Any One Reference to the Others with 20 V p-p, 10 kHz Sine Wave Applied Effect of All 0s to All 1s Code Transition on Nonselected DACs Feedthrough to Any DAC Output with FSIN High and Square Wave Applied to SDIN and SCLK VREF = 6 V rms, 1 kHz Sine Wave All 1s Loaded to the DAC. VREF = 0 V. Output Op Amp Is ADOP07
AC Performance Characteristics Biased Mode
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density @ 1 kHz
(VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = 1.23 V; AGND = 0 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; TA = TMIN to TMAX, unless otherwise noted. These characteristics are included for Design Guidance and are not subject to test.)
A Grade 3.5 35 -70 100 40 5 -76 20 Units s typ nV-s typ dB max pF max pF max nV-s typ dB typ nV/Hz typ All 1s Loaded to DAC. VIOUT2 = 0 V; VREF = 0 V Test Conditions/Comments To 0.01% of Full-Scale Range. VREF = 0 V. DAC Latch Alternately Loaded with all 0s and all 1s. Measured with VIOUT2 = 0 V and VREF = 0 V. DAC Register Alternately Loaded with all 0s and all 1s. DAC Latch Loaded with all 0s. All 1s Loaded to DAC All 0s Loaded to DAC Feedthrough to Any DAC Output with FSIN HIGH and a Square Wave Applied to SDIN and CLKIN
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REV. A
AD7564 Timing Specifications1
Parameter t1 t2 t3 t4 t5 t6 t7 t82 t9 180 80 80 50 50 10 125 100 80
(TA = TMIN to TMAX unless otherwise noted)
Units ns min ns min ns min ns min ns min ns min ns min ns max ns min Description CLKIN Cycle Time CLKIN High Time CLKIN Low Time FSIN Setup Time Data Setup Time Data Hold Time FSIN Hold Time SDOUT Valid After CLKIN Falling Edge LDAC, CLR Pulse Width
Limit at Limit at VDD = +3 V to +3.6 V VDD = +4.75 V to +5.25 V 100 40 40 30 30 5 90 70 40
3
NOTES 1 Not production tested. Guaranteed by characterization at initial product release. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V for a VDD of 5 V and from a voltage level 1.35 V for a VDD of 3.3 V. 2 t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with a VDD of 5 V and 0.6 V or 2.1 V for a VDD of 3.3 V.
t1
CLKIN(I)
t4
FSIN(I)
t2
t3 t7
t5 t6
SDIN(I) DB15 DB0
t8
SDOUT(O) DB15 DB0
LDAC, CLR
t9
Figure 1. Timing Diagram
1.6mA
IOL
TO OUTPUT PIN +1.6V CL 50pF
200A
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
REV. A
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AD7564
ABSOLUTE MAXIMUM RATINGS 1 (TA = +25C unless otherwise noted) PIN CONFIGURATION DIP, SOIC and SSOP Packages
DGND IOUT2 C VDD IOUT1 C RFB C VREF C IOUT2 D IOUT1 D RFB D VREF D SDOUT CLR LDAC FSIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 IOUT2 B 27 AGND 26 NC 25 IOUT1 B 24 RFB B 23 VREF B
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V IOUT1 to DGND . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V IOUT2 to DGND . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . -0.3 V to VDD + 0.3 V VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA Operating Temperature Range Commercial Plastic (A, B Versions). . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C DIP Package, Power Dissipation . . . . . . . . . . . . . . . . . 875 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 75C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . 260C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 75C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . 260C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 900 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 100C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
IOUT2 A TOP VIEW 21 IOUT1 A (Not to Scale) 20 19 18 17 16 15 RFB A VREF A A0 A1 C OLKIN SDIN
AD7564
22
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7564 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD7564BN AD7564BR AD7564BRS AD7564AR-B AD7564ARS-B
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Linearity Nominal Error (LSBs) Supply Voltage 0.5 0.5 0.5 1 1 +5 V +5 V +5 V +3.3 V to +5 V +3.3 V to +5 V
Package Option* N-28 R-28 RS-28 R-28 RS-28
*N = DIP; R = SOIC; RS = SSOP.
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REV. A
AD7564
PIN DESCRIPTIONS
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Mnemonic DGND IOUT2C VDD IOUT1C RFBC VREFC IOUT2D IOUT1D RFBD VREFD SDOUT CLR LDAC FSIN
Description Digital Ground. IOUT2 terminal for DAC C. This should normally connect to the signal ground of the system. Positive power supply. This is +5 V 5%. IOUT1 terminal for DAC C. Feedback resistor for DAC C. DAC C reference input. IOUT2 terminal for DAC D. This should normally connect to the signal ground of the system. IOUT1 terminal for DAC D. Feedback resistor for DAC D. DAC D reference input. This shift register output allows multiple devices to be connected in a daisy chain configuration. Asynchronous CLR input. When this input is taken low, all DAC latches are loaded with all 0s. Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the input latches. Level-triggered control input (active low). This is the frame synchronization signal for the input data. When FSIN goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bits are valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN goes low. Serial data input. The device accepts a 16-bit word. DB0 and DB1 are DAC select bits. DB2 and DB3 are device address bits. DB4 to DB15 contain the 12-bit data to be loaded to the selected DAC. Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Device address pin. This input in association with A0 gives the device an address. If DB2 and DB3 of the serial input stream do not correspond to this address, the data which follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this. Device address pin. This input in association with A1 gives the device an address. DAC A reference input. Feedback resistor for DAC A. IOUT1 terminal for DAC A. IOUT2 terminal for DAC A. This should normally connect to the signal ground of the system. DAC B reference input. Feedback resistor for DAC B. IOUT1 terminal for DAC B. No Connect pin. This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system. IOUT2 terminal for DAC B. This should normally connect to the signal ground of the system.
3
15
SDIN
16 17
CLKIN A1
18 19 20 21 22 23 24 25 26 27 28
A0 VREFA RFBA IOUT1A IOUT2A VREFB RFBB IOUT1B N/C AGND IOUT2B
REV. A
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AD7564
TERMINOLOGY Relative Accuracy Output Voltage Settling Time
Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of full-scale reading.
Differential Nonlinearity
This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For the AD7564, it is specified with the AD843 as the output op amp.
Digital to Analog Glitch Impulse
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Gain Error
This is the amount of charge injected into the analog output when the inputs change state. It is normally specified as the area of the glitch in either pA-secs or nV-secs, depending upon whether the glitch is measured as a current or voltage signal. It is measured with the reference input connected to AGND and the digital inputs toggled between all 1s and all 0s.
AC Feedthrough Error
Gain error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all 1s in the DAC after offset error has been adjusted out and is expressed in Least Significant Bits. Gain error is adjustable to zero with an external potentiometer.
Output Leakage Current
This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT terminal, when all 0s are loaded in the DAC.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input signal from one DAC's reference input which appears at the output of any other DAC in the device and is expressed in dBs.
Digital Crosstalk
Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s. This is a combination of the switch leakage current and the ladder termination resistor current. The IOUT2 leakage current is typically equal to that in IOUT1.
Output Capacitance
The glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the Digital Crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up at on the IOUT pin and subsequently on the op amp output. This noise is digital feedthrough.
This is the capacitance from the IOUT1 pin to AGND.
Table I. AD7564 Loading Sequence
DB15 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A1 A0 DS1
DB0 DS0
Table II. DAC Selection
DS1 0 0 1 1
DS0 0 1 0 1
Function DAC A Selected DAC B Selected DAC C Selected DAC D Selected
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REV. A
Typical Performance Curves-AD7564
0.5 NORMAL MODE OF OPERATION VDD = +5V TA = +25C 0.4 0.4 0.5 NORMAL MODE OF OPERATION VDD = +5V TA = +25C
DNL - LSBs
0.2
INL - LSBs
0.3
0.3
0.2
0.1
0.1
0.0 2 4 6 VREF - Volts 8 10
0.0 2 4 6 VREF - Volts 8 10
Figure 3. Differential Nonlinearity Error vs. VREF (Normal Mode)
Figure 6. Integral Nonlinearity Error vs. VREF (Normal Mode)
0 -10 -20 VREFC = 20V p-p SINE WAVE ALL OTHER REFERENCE INPUTS = 0V DAC C LOADED WITH ALL 1s ALL OTHER DACs LOADED WITH ALL 0s
0 -10 -20
VOUTB/VOUTC - dBs
VREFB = 0V ALL OTHER REFERENCE INPUTS = 20V p-p SINE WAVE DAC B LOADED WITH ALL 0s ALL OTHER DACs LOADED WITH ALL 1s
VOUTB/VOUTC - dBs
-30 -40 -50 -60 -70 -80 -90 103 104 105 FREQUENCY - Hz 106
-30 -40 -50 -60 -70 -80 -90 103 104 105 FREQUENCY - Hz 106
Figure 4. Channel-to-Channel Isolation (1 DAC to 1 DAC)
Figure 7. Channel-to-Channel Isolation (1 DAC to All Other DACs)
-50 NORMAL MODE OF OPERATION VDD = +5V VIN = +6V rms OP AMP = AD713 TA = +25C
GAIN - dB
0 -10 -20 -30 -40 -50 DAC LOADED WITH ALL 0s -60 -70 -80 VDD = +5V TA = +25C VIN = 20V p-p OP AMP = AD711
DAC LOADED WITH ALL 1s
-60
THD - dBs
-70
-80
-90
-90 -100
-100 102
1k
10k
103 104 FREQUENCY - Hz
105
100k FREQUENCY - Hz
1M
10M
Figure 5. Total Harmonic Distortion vs. Frequency (Normal Mode)
Figure 8. Multiplying Frequency Response vs. Digital Code (Normal Mode)
REV. A
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AD7564
2.0 1.8 1.6 1.4 INL - LSBs 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 VDD = +3.3V TA = +25C OP AMP = AD820 VREF = +1.23V (AD589) 2.0 1.8 1.6 1.4 VDD = +3.3V TA = +25C OP AMP = AD820 VREF = +1.23V (AD589)
DNL - LSBs
0.4 1.4
1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2
0.6 0.8 1.0 |VREF - VBIAS| - Volts
1.2
0.4
0.6 0.8 1.0 |VREF - VBIAS| - Volts
1.2
1.4
Figure 9. Integral Nonlinearity Error vs. VREF (Biased Mode)
Figure 12. Differential Nonlinearity Error vs. VREF (Biased Mode)
2.0 1.8 1.6 1.4
DNL - LSBs
INL - LSBs
2.0
VDD = +5V TA = +25C OP AMP = AD820 VBIAS = +1.23V (AD589)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2
VDD = +5V TA = +25C OP AMP = AD820 VBIAS = +1.23V (AD589)
1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2
0.4
0.6 0.8 1.0 |VREF - VBIAS| - Volts
1.2
1.4
0.4
0.6 0.8 1.0 |VREF - VBIAS| - Volts
1.2
1.4
Figure 10. Integral Nonlinearity Error vs. VREF (Biased Mode)
Figure 13. Differential Nonlinearity Error vs. VREF (Biased Mode)
0.2
0.4
0.1
0.3
LINEARITY ERROR - LSBs
NORMAL MODE VDD = +5V TA = +25C VREF = 10V
LINEARITY ERROR - LSBs
0.0 -0.1
0.2
-0.2 -0.3 VDD = +3.3V TA = +25C VBIAS = 1.23V VREF = 0V 0 1024 2048 CODE - LSBs 3072 4095
0.1
0.0
-0.4 -0.5
-0.1 0 1024 2048 CODE - LSBs 3072 4095
Figure 11. All Codes Linearity Plot (Biased Mode)
Figure 14. All Codes Linearity Plot (Normal Mode)
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REV. A
AD7564
GENERAL DESCRIPTION D/A Section
The AD7564 contains four 12-bit current output D/A converters. A simplified circuit diagram for one of the D/A converters is shown in Figure 15.
V REF R R R
Bringing the CLR line low resets the DAC latches to all 0s. The input latches are not affected so that the user can revert to the previous analog output if desired.
CLKIN FSIN SDIN 16-BIT INPUT SHIFT REGISTER SDOUT
2R C B
2R A
2R S9
2R S8
2R
2R S0
2R R/2 R FB I OUT1 I OUT2
Figure 16. Input Logic
UNIPOLAR BINARY OPERATION (2-Quadrant Multiplication)
3
SHOWN FOR ALL 1s ON DAC
Figure 15. Simplified D/A Circuit Diagram
Figure 17 shows the standard unipolar binary connection diagram for one of the DACs in the AD7564. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Resistors R1 and R2 allow the user to adjust the DAC gain error. Offset can be removed by adjusting the output amplifier offset voltage.
R2 10 RFBA R1 20 VIN VREFA DAC A IOUT1A IOUT2A C1 A1 A1: AD707 AD711 AD843 AD845 VOUT
A segmented scheme is used whereby the 2 MSBs of the 12-bit data word are decoded to drive the three switches A, B and C. The remaining 10 bits of the data word drive the switches S0 to S9 in a standard R-2R ladder configuration. Each of the switches A to C steers 1/4 of the total reference current with the remaining current passing through the R-2R section. All DACs have separate VREF, IOUT1, IOUT2 and RFB pins. When an output amplifier is connected in the standard configuration of Figure 17, the output voltage is given by:
AD7564
SIGNAL GND
NOTES 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5-15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
V OUT = D xV REF
where D is the fractional representation of the digital word loaded to the DAC. Thus, in the AD7564, D can be set from 0 to 4095/4096.
Interface Section
Figure 17. Unipolar Binary Operation
The AD7564 is a serial input device. Three input signals control the serial interface. These are FSIN, CLKIN and SDIN. The timing diagram is shown in Figure 1. Data applied to the SDIN pin is clocked into the input shift register on each falling edge of CLKIN. SDOUT is the shift register output. It allows multiple devices to be connected in a daisy chain fashion with the SDOUT pin of one device connected to the SDIN of the next device. FSIN is the frame synchronization for the device. When the sixteen bits have been received in the input shift register, DB2 and DB3 (A0 and A1) are checked to see if they correspond to the state on pins A0 and A1. If it does, then the word is accepted. Otherwise, it is disregarded. This allows the user to address a number of AD7564s in a very simple fashion. DB1 and DB0 of the 16-bit word determine which of the four DAC input latches is to be loaded. When the LDAC line goes low, all four DAC latches in the device are simultaneously loaded with the contents of their respective input latches and the outputs change accordingly.
A1 should be chosen to suit the application. For example, the AD707 is ideal for very low bandwidth applications while the AD843 and AD845 offer very fast settling time in wide bandwidth applications. Appropriate multiple versions of these amplifiers can be used with the AD7564 to reduce board space requirements. The code table for Figure 17 is shown in Table III.
Table III. Unipolar Binary Code Table
Digital Input MSB . . . LSB 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Analog Output (VOUT as Shown in Figure 17) -VREF (4095/4096) -VREF (2049/4096) -VREF (2048/4096) -VREF (2047/4096) -VREF (1/4096) -VREF (0/4096) = 0
NOTE Nominal LSB size for the circuit of Figure 17 is given by: V REF (1/4096).
REV. A
-11-
AD7564
BIPOLAR OPERATION 4-Quadrant Multiplication)
Figure 18 shows the standard connection diagram for bipolar operation of any one of the DACs in the AD7564. The coding is offset binary as shown in Table IV. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. To maintain the gain error specifications, resistors R3, R4 and R5 should be ratio matched to 0.01%.
R4 20k R2 10 RFBA R1 20 VIN DAC A VREFA IOUT1A IOUT2A C1 A1 R3 10k A2 VOUT R4 20 20k R5
In the current mode circuit of Figure 19, IOUT2 and hence IOUT1, is biased positive by an amount VBIAS. For the circuit to operate correctly, the DAC ladder termination resistor must be connected internally to IOUT2. This is the case with the AD7564. The output voltage is given by:
R V OUT = D x FB x (V RDAC
BIAS -V IN
) +V BIAS
As D varies from 0 to 4095/4096, the output voltage varies from VOUT = VBIAS to VOUT = 2 VBIAS - VIN. VBIAS should be a low impedance source capable of sinking and sourcing all possible variations in current at the IOUT2 terminal without any problems.
Voltage Mode Circuit
AD7564
NOTES: SIGNAL GND
1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5-15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 18. Bipolar Operation (4-Quadrant Multiplication)
Table IV. Bipolar (Offset Binary) Code Table
Digital Input MSB . . . LSB 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Analog Output (VOUT as Shown in Figure 18) -VREF (2047/2048) -VREF (1/2048) -VREF (0/2048 = 0) -VREF (1/2048) -VREF (2047/2048) -VREF (2048/2048) = -VREF
Figure 20 shows DAC A of the AD7564 operating in the voltage-switching mode. The reference voltage, VIN is applied to the IOUT1 pin, IOUT2 is connected to AGND and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage; making single supply operation possible. The output from the DAC is a voltage at a constant impedance (the DAC ladder resistance). Thus, an op amp is necessary to buffer the output voltage. The reference voltage input no longer sees a constant input impedance, but one which varies with code. So, the voltage input should be driven from a low impedance source. It is important to note that VIN is limited to low voltages because the switches in the DAC no longer have the same sourcedrain voltage. As a result, their on-resistance differs and this degrades the integral linearity of the DAC. Also, VIN must not go negative by more than 0.3 volts or an internal diode will turn on, causing possible damage to the device. This means that the full-range multiplying capability of the DAC is lost.
R1 RFBA R2
NOTE Nominal LSB size for the circuit of Figure 18 is given by: V REF (1/2048).
SINGLE SUPPLY APPLICATIONS
The "-B" versions of the AD7564 are specified and tested for single supply applications. Figure 19 shows a typical circuit for operation with a single +3.3 V to +5 V supply.
RFBA IOUT1A VIN VREFA DAC A IOUT2A A1 VOUT
VIN
IOUT1A IOUT2A DAC A VREFA
A1
VOUT
AD7564
NOTES 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5-15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
AD7564
Figure 20. Single Supply Voltage Switching Mode Operation
VBIAS NOTES: 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5-15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 19. Single Supply Current Mode Operation
-12-
REV. A
AD7564
MICROPROCESSOR INTERFACING AD7564 to 80C51 Interface AD7564 to 68HC11 Interface
A serial interface between the AD7564 and the 80C51 microcontroller is shown in Figure 21. TXD of the 80C51 drives SCLK of the AD7564 while RXD drives the serial data line of the part. The FSIN signal is derived from the port line P3.3. The 80C51 provides the LSB of its SBUF register as the first bit in the serial data stream. Therefore, the user will have to ensure that the data in the SBUF register is arranged correctly so that the data word transmitted to the AD7564 corresponds to the loading sequence shown in Table I. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 80C51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7564, P3.3 is left low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7564. When the second serial transfer is complete, the P3.3 line is taken high. Note that the 80C51 outputs the serial data byte in a format which has the LSB first. The AD7564 expects the MSB first. The 80C51 transmit routine should take this into account.
Figure 22 shows a serial interface between the AD7564 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of the AD7564 while the MOSI output drives the serial data line of the AD7564. The FSIN signal is derived from a port line (PC7 shown). For correct operation of this interface, the 68HC11 should be configured such that its CPOL bit is a 0 and its CPHA bit is a 1. When data is to be transmitted to the part, PC7 is taken low. When the 68HC11 is configured like this, data on MOSI is valid on the falling edge of SCK. The 68HC11 transmits its serial data in 8-bit bytes (MSB first), with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7564 , PC7 is left low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7564. When the second serial transfer is complete, the PC7 line is taken high.
3
AD7564*
64HC11*
PC5 CLR LDAC FSIN SCLK SDIN
AD7564*
80C51*
P3.5 P3.4 P3.3 TXD RXD CLR LDAC FSIN SCLK
PC6 PC7 SCK MOSI
*ADDITIONAL PINS OMMITTED FOR CLARITY
SDIN
Figure 22. AD7564 to 64HC11 Interface
*ADDITIONAL PINS OMMITTED FOR CLARITY
Figure 21. AD7564 to 80C51 Interface
LDAC and CLR on the AD7564 are also controlled by 80C51 port outputs. The user can bring LDAC low after every two bytes have been transmitted to update the DAC which has been programmed. Alternatively, it is possible to wait until all the input registers have been loaded (sixteen byte transmits) and then update the DAC outputs.
In Figure 22, LDAC and CLR are controlled by the PC6 and PC5 port outputs. As with the 80C51, each DAC of the AD7564 can be updated after each two-byte transfer, or else all DACs can be simultaneously updated. This interface is suitable for both 3 V and 5 V versions of the 68HC11 microcontroller.
REV. A
-13-
AD7564
AD7564 to ADSP-2101/ADSP-2103 Interface
Figure 23 shows a serial interface between the AD7564 and the ADSP-2101/ADSP-2103 digital signal processors. The ADSP2101 operates from 5 V while the ADSP-2103 operates from 3 V supplies. These processors are set up to operate in the SPORT Transmit Alternate Framing Mode. The following DSP conditions are recommended: Internal SCLK; Active low Framing Signal; 16-bit word length. Transmission is initiated by writing a word to the TX register after the SPORT has been enabled. The data is then clocked out on every rising edge of SCLK after TFS goes low. TFS stays low until the next data transfer.
AD7564*
TMS320C25*
+5V
CLR XF FSX DX CLKX LDAC FSIN SDIN CLKIN
CLOCK GENERATION *ADDITIONAL PINS OMMITTED FOR CLARITY
AD7564*
ADSP-2101/ ADSP-2103
+5V
Figure 24. AD7564 to TMS320C25 Interface
CLR
APPLICATION HINTS Output Offset
FO TFS DT SCLK
LDAC FSIN SDIN CLKIN
*ADDITIONAL PINS OMMITTED FOR CLARITY
Figure 23. AD7564 to ADSP-2101/ADSP-2103 Interface
AD7564 to TMS320C25 Interface
Figure 24 shows an interface circuit for the TMS320C25 digital signal processor. The data on the DX pin is clocked out of the processor's Transmit Shift Register by the CLKX signal. Sixteen-bit transmit format should be chosen by setting the FO bit in the ST1 register to 0. The transmit operation begins when data is written into the data transmit register of the TMS320C25. This data will be transmitted when the FSX line goes low while CLKX is high or going high. The data, starting with the MSB, is then shifted out to the DX pin on the rising edge of CLKX. When all bits have been transmitted, the user can update the DAC outputs by bringing the XF output flag low.
CMOS D/A converters in circuits such as Figures 17, 18 and 19 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier. The maximum amplitude of this error, which adds to the D/A converter nonlinearity, depends on VOS, where VOS is the amplifier input offset voltage. For the AD7564 to maintain specified accuracy with VREF at 10 V, it is recommended that VOS be no greater than 500 V, or (50 x 10-6) x (VREF), over the temperature range of operation. Suitable amplifiers include the ADOP-07, ADOP-27, AD711, AD845 or multiple versions of these.
Temperature Coefficients
The gain temperature coefficient of the AD7564 has a maximum value of 5 ppm/C and a typical value of 2 ppm/C. This corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively over a 100C temperature range. When trim resistors R1 and R2 are used to adjust full scale in Figures 17 and 18, their temperature coefficients should be taken into account. For further information see "Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs," Application Note, Publication Number E630c-5-3/86, available from Analog Devices.
High Frequency Considerations
The output capacitances of the AD7564 DACs work in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. This is shown as C1 in Figures 17 and 18.
-14-
REV. A
AD7564
APPLICATIONS Programmable State Variable Filter
In the circuit of Figure 25: C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to each DAC). Resonant Frequency, fO = 1/(2 R3C1) Quality Factor, Q = (R6/R8) x (R2/R5) Bandpass Gain, AO = -R2/R1 Using the values shown in Figure 25, the Q range is 0.3 to 5 and the fO range is 0 to 12 kHz.
The AD7564 with its multiplying capability and fast settling time is ideal for many types of signal conditioning applications. The circuit of Figure 25 shows its use in a state variable filter design. This type of filter has three outputs: low pass, high pass and bandpass. The particular version shown in Figure 25 uses the AD7564 to control the critical parameters fO, Q and AO. Instead of several fixed resistors, the circuit uses the DAC equivalent resistances as circuit elements. Thus, R1 in Figure 25 is controlled by the 12-bit digital word loaded to DAC A of the AD7564. This is also the case with R2, R3 and R4. The fixed resistor R5 is the feedback resistor, RFBB. DAC Equivalent Resistance, REQ = (RLADDER x 4096)/N where: RLADDER is the DAC ladder resistance N is the DAC Digital Code in Decimal (0 < N < 4096)
3
C3 10pF
R8 30k R6 10k A1 A2
R7 30k
C1 1000pF
C2 1000pF
HIGH PASS OUTPUT
A3
A4
LOW PASS OUTPUT
IOUT1A
IOUT1B R5
RFBB
VREFB
VREFC
IOUT1C
VREFD
IOUT1D
BAND PASS OUTPUT
VIN
VREFA
DAC A (R1)
DAC B (R2)
DAC C (R3)
DAC D (R4)
AD7564
IOUT2A IOUT2B AGND IOUT2C IOUT2D
NOTES 1. A1, A2, A3, A4, : 1/4 X AD713. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN AND BANDWIDTH LIMITATIONS.
Figure 25. Programmable 2nd Order State Variable Filter
REV. A
-15-
AD7564
MECHANICAL INFORMATION
Dimensions shown in inches and (mm).
28-Pin DIP (N-28)
C1977-18-10/94
0.042 (1.067) 0.018 (0.457)
28 15 0.550 (13.97) 0.530 (13.462) 1 0.200 (5.080) MAX 1.450 (36.83) 1.440 (36.576) 14 0.606 (15.39) 0.594 (15.09) 0.160 (4.07) 0.140 (3.56) 15 o 0.020 (0.508) 0.015 (0.381) 0.105 (2.67) 0.095 (2.41) 0.065 (1.65) 0.045 (1.14) 0.175 (4.45) 0.120 (3.05) 0.012 (0.305) 0.008 (0.203) 0o
LEADS ARE SOLDER DIPPED OR TIN-PLATED ALLOY 42 OR COPPER.
28-Lead SOIC (R-28)
28
15
0.299 (7.60) 0.291 (7.39) PIN 1 1
0.414 (10.52) 0.398 (10.10) 14
0.708 (18.02) 0.696 (17.67) 0.096 (2.44) 0.089 (2.26) 0.01 (0.254) 0.006 (0.15)
0.03 (0.76) 0.02 (0.51)
0.050 (1.27) BSC
0.019 (0.49) 0.014 (0.35)
0.013 (0.32) 0.009 (0.23)
1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. SOIC LEADS WILL BE EITHER TIN PLATED OF SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
28-Lead SSOP (RS-28)
28
15 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) 1 14
PIN 1
0.407 (10.34) 0.397 (10.08)
0.07 (1.78) 0.066 (1.67)
0.008 (0.203) 0.002 (0.050)
8 0 0.009 (0.229) 0.005 (0.127) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.0256 (0.65) BSC
0.03 (0.762) 0.022 (0.558)
-16-
REV. A
PRINTED IN U.S.A.

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